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ICCAD
2007
IEEE
111views Hardware» more  ICCAD 2007»
15 years 7 months ago
Exploiting STI stress for performance
— Starting at the 65nm node, stress engineering to improve performance of transistors has been a major industry focus. An intrinsic stress source – shallow trench isolation –...
Andrew B. Kahng, Puneet Sharma, Rasit Onur Topalog...
ICCAD
2007
IEEE
144views Hardware» more  ICCAD 2007»
15 years 7 months ago
Voltage island-driven floorplanning
— Energy efficiency has become one of the most important issues to be addressed in today’s System-on-a-Chip (SoC) designs. One way to lower the power consumption is to reduce ...
Qiang Ma, Evangeline F. Y. Young
ICCAD
2006
IEEE
152views Hardware» more  ICCAD 2006»
15 years 7 months ago
Fast and robust quadratic placement combined with an exact linear net model
— This paper presents a robust quadratic placement approach, which offers both high-quality placements and excellent computational efficiency. The additional force which distrib...
Peter Spindler, Frank M. Johannes
SOSP
2005
ACM
15 years 7 months ago
Implementing declarative overlays
Overlay networks are used today in a variety of distributed systems ranging from file-sharing and storage systems to communication infrastructures. However, designing, building a...
Boon Thau Loo, Tyson Condie, Joseph M. Hellerstein...
ISPASS
2009
IEEE
15 years 5 months ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...