58 search results - page 10 / 12 » Routing in a New 2-Dimensional FPGA FPIC Routing Architectur... |
66
Voted
FPL
2005
Springer
15 years 3 months ago
2005
Springer
Modern heterogeneous FPGAs contain “hard” specificpurpose structures such as blocks of memory and multipliers in addition to the completely flexible “soft” programmable ...
101
Voted
FPGA
2004
ACM
15 years 3 months ago
2004
ACM
The cost functions used to evaluate logic synthesis transformations for FPGAs are far removed from the final speed and routability determined after placement, routing and timing a...
96
Voted
INFOCOM
2010
IEEE
14 years 8 months ago
2010
IEEE
It is becoming apparent that the next generation IP route lookup architecture needs to achieve speeds of 100Gbps and beyond while supporting both IPv4 and IPv6 with fast real-time ...
97
Voted
TVLSI
2008
14 years 10 months ago
2008
This paper describes Glitchless, a circuit-level technique for reducing power in FPGAs by eliminating unnecessary logic transitions called glitches. This is done by adding program...
67
Voted
NOCS
2007
IEEE
15 years 4 months ago
2007
IEEE
In this paper we present a new clustered mesh FPGA architecture where each cluster local interconnect is implemented as an MFPGA tree network [6]. Unlike previous clustered mesh a...