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» Routing in a New 2-Dimensional FPGA FPIC Routing Architectur...
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76
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TVLSI
2008
106views more  TVLSI 2008»
14 years 10 months ago
New Non-Volatile Memory Structures for FPGA Architectures
A new set of programmable elements (PEs) using a new non-volatile device for use with routing switches and logical elements within a field-programmable gate array (FPGA) is describ...
David Choi, Kyu Choi, John D. Villasenor
101
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FPGA
2005
ACM
215views FPGA» more  FPGA 2005»
15 years 3 months ago
Design, layout and verification of an FPGA using automated tools
Creating a new FPGA is a challenging undertaking because of the significant effort that must be spent on circuit design, layout and verification. It currently takes approximately ...
Ian Kuon, Aaron Egier, Jonathan Rose
90
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ICES
1998
Springer
131views Hardware» more  ICES 1998»
15 years 2 months ago
Aspects of Digital Evolution: Geometry and Learning
In this paper we present a new chromosome representation for evolving digital circuits. The representation is based very closely on the chip architecture of the Xilinx 6216 FPGA. W...
Julian F. Miller, Peter Thomson
GLVLSI
2008
IEEE
197views VLSI» more  GLVLSI 2008»
14 years 10 months ago
Efficient tree topology for FPGA interconnect network
This paper presents an improved Tree-based architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butterfly-FatTree topolo...
Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib ...
79
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ICCAD
2006
IEEE
125views Hardware» more  ICCAD 2006»
15 years 7 months ago
Performances improvement of FPGA using novel multilevel hierarchical interconnection structure
This paper presents a new Multilevel hierarchical FPGA (MFPGA) architecture that unifies two unidirectional programmable networks: A predictible downward network based on the But...
Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Ha...