Sciweavers

58 search results - page 9 / 12
» Routing in a New 2-Dimensional FPGA FPIC Routing Architectur...
Sort
View
79
Voted
FPL
2007
Springer
178views Hardware» more  FPL 2007»
15 years 4 months ago
Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support
This paper introduces a software supported methodology for exploring/evaluating 3D FPGA architectures. Two new CAD tools are developed: (i) the 3DPRO for placement and routing on ...
Kostas Siozios, Kostas Sotiriadis, Vasilis F. Pavl...
EURODAC
1995
IEEE
133views VHDL» more  EURODAC 1995»
15 years 1 months ago
Tree restructuring approach to mapping problem in cellular-architecture FPGAs
A new technique for mapping combinational circuits to Fine-Grain Cellular-Architecture FPGAs is presented. The proposed tree restructuring algorithm preserves local connectivity a...
Naveen Ramineni, Malgorzata Chrzanowska-Jeske, Nav...
FPL
2005
Springer
96views Hardware» more  FPL 2005»
15 years 3 months ago
Dynamic Reconfiguration with hardwired Networks-on-Chip on future FPGAs
Due to their layered approach, Networks-on-Chip (NoC) are a promising communication backbone in the field of heterogeneous dynamically reconfigurable systems. In this paper a fu...
Ronald Hecht, Stephan Kubisch, Andreas Herrholtz, ...
63
Voted
DAC
2005
ACM
15 years 11 months ago
Architecture-adaptive range limit windowing for simulated annealing FPGA placement
Previous research has shown both theoretically and practically that simulated annealing can greatly benefit from the incorporation of an adaptive range limiting window to control ...
Kenneth Eguro, Scott Hauck, Akshay Sharma
89
Voted
FPGA
1999
ACM
115views FPGA» more  FPGA 1999»
15 years 2 months ago
Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density
In this paper, we investigate the speed and area-efficiency of FPGAs employing “logic clusters” containing multiple LUTs and registers as their logic block. We introduce a ne...
Alexander Marquardt, Vaughn Betz, Jonathan Rose