55 search results - page 2 / 11 » Run-time compaction of FPGA designs |
RTSS
2006
IEEE
15 years 3 months ago
2006
IEEE
Modern FPGA devices, which include (multiple) processor core(s) as diffused IP on the silicon die, provide an excellent platform for developing custom multiprocessor systems-on-pr...
FPL
1997
Springer
15 years 1 months ago
1997
Springer
Controllers for dynamically recon gurable FPGAs that are capable of supporting multiple independent tasks simultaneously need to be able to place designs at run{time when the seque...
ISQED
2007
IEEE
15 years 3 months ago
2007
IEEE
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
FPGA
2008
ACM
14 years 11 months ago
2008
ACM
A design tool for routing channel segmentation in islandstyle FPGAs is presented. Given the FPGA architecture parameters and a set of benchmark designs, the tool optimizes routing...
IDEAL
2003
Springer
15 years 2 months ago
2003
Springer
Mining frequent patterns has been a topic of active research because it is computationally the most expensive step in association rule discovery. In this paper, we discuss the use ...