191 search results - page 4 / 39 » Run-time modeling and estimation of operating system power c... |
125
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PATMOS
2000
Springer
15 years 4 months ago
2000
Springer
Abstract. Reduction of chip packaging and cooling costs for deep sub-micron SystemOn-Chip (SOC) designs is an emerging issue. We present a simulation-based methodology able to real...
108
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IPPS
2006
IEEE
15 years 6 months ago
2006
IEEE
Current electronic system design requires to be concerned with power consumption consideration. However, in a lot of design tools, the application power consumption budget is esti...
139
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CODES
2003
IEEE
15 years 5 months ago
2003
IEEE
In this paper, we describe a new methodology based on game theory for minimizing the average power of a circuit during scheduling in behavioral synthesis. The problem of schedulin...
76
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DATE
2000
IEEE
15 years 4 months ago
2000
IEEE
Designs which do not fully utilize their arithmetic datapath components typically exhibit a significant overhead in power consumption. Whenever a module performs an operation who...
FPL
2010
Springer
14 years 10 months ago
2010
Springer
The paper describes application of the clock-gating techniques, often used in ASIC designs, to the field of FPGAbased systems. The clock-gating techniques are used to reduce the to...