36 search results - page 2 / 8 » Runtime and quality tradeoffs in FPGA placement and routing |
DAC
2008
ACM
15 years 10 months ago
2008
ACM
FPGA application developers often attempt to use pipelining, Cslowing and retiming to improve the performance of their designs. Unfortunately, such registered netlists present a f...
FPGA
1999
ACM
15 years 1 months ago
1999
ACM
The demand for high-speed FPGA compilation tools has occurred for three reasons: first, as FPGA device capacity has grown, the computation time devoted to placement and routing h...
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Voted
FPGA
2003
ACM
15 years 2 months ago
2003
ACM
To truly exploit FPGAs for rapid turn-around development and prototyping, placement times must be reduced to seconds; latebound, reconfigurable computing applications may demand p...
DAC
2006
ACM
15 years 10 months ago
2006
ACM
Since performance on FPGAs is dominated by the routing architecture rather than wirelength, we propose a new architecture-aware approach to initial FPGA placement that models the ...
DAC
2009
ACM
15 years 1 months ago
2009
ACM
Structured ASICs have recently emerged as an exciting alternative to ASIC or FPGA design style as they provide a new trade-off between the high performance of ASIC design and low ...