36 search results - page 4 / 8 » Runtime and quality tradeoffs in FPGA placement and routing |
101
Voted
FPL
2001
Springer
15 years 1 months ago
2001
Springer
In this paper we present a new method of integrating the placement and routing stages in the physical design of channel-based architectures, and present the first implementation o...
FPGA
2005
ACM
15 years 3 months ago
2005
ACM
Logic duplication is an effective method for improving circuit performance. In this paper we present an algorithm named SPD that performs simultaneous placement and duplication to...
FPGA
2000
ACM
15 years 1 months ago
2000
ACM
In this paper we introduce a new Simulated Annealingbased timing-driven placement algorithm for FPGAs. This paper has three main contributions. First, our algorithm employs a nove...
FPGA
2004
ACM
15 years 2 months ago
2004
ACM
In this work, we parameterize and explore the interconnect structure of pipelined FPGAs. Specifically, we explore the effects of interconnect register population, length of regist...
85
Voted
ICCTA
2007
IEEE
15 years 1 months ago
2007
IEEE
In this paper, we propose a placement method for islandstyle FPGAs, based on fast yet very good initial placement followed by refinement using ultra-low temperature Simulated Anne...