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» Runtime and quality tradeoffs in FPGA placement and routing
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FCCM
2005
IEEE
139views VLSI» more  FCCM 2005»
15 years 3 months ago
A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation
Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
MAM
2006
95views more  MAM 2006»
14 years 9 months ago
Stochastic spatial routing for reconfigurable networks
FPGA placement and routing is time consuming, often serving as the major obstacle inhibiting a fast edit-compile-test loop in prototyping and development and the major obstacle pr...
André DeHon, Randy Huang, John Wawrzynek
ASPDAC
2007
ACM
99views Hardware» more  ASPDAC 2007»
15 years 1 months ago
DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm
Abstract - This paper presents a fast and accurate global routing algorithm, DpRouter, based on two efficient techniques: (1) dynamic pattern routing (Dpr), and (2) segment movemen...
Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Lei He, ...
77
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IPTPS
2005
Springer
15 years 3 months ago
Evaluating DHT-Based Service Placement for Stream-Based Overlays
Stream-based overlay networks (SBONs) are one approach to implementing large-scale stream processing systems. A fundamental consideration in an SBON is that of service placement, ...
Peter R. Pietzuch, Jeffrey Shneidman, Jonathan Led...
ICCAD
2006
IEEE
152views Hardware» more  ICCAD 2006»
15 years 6 months ago
Fast and robust quadratic placement combined with an exact linear net model
— This paper presents a robust quadratic placement approach, which offers both high-quality placements and excellent computational efficiency. The additional force which distrib...
Peter Spindler, Frank M. Johannes