36 search results - page 7 / 8 » Runtime and quality tradeoffs in FPGA placement and routing |
88
Voted
DAC
2006
ACM
15 years 10 months ago
2006
ACM
Both technology mapping and circuit clustering have a large impact on FPGA designs in terms of circuit performance, area, and power dissipation. Existing FPGA design flows carry o...
AHS
2006
IEEE
15 years 3 months ago
2006
IEEE
Domain-specific reconfigurable arrays have shown to provide an efficient trade-off between flexibility of FPGA and performance of ASIC circuit. Nonetheless, the design of these he...
120
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ISPD
2012
ACM
13 years 5 months ago
2012
ACM
We propose a new multilevel framework for large-scale placement called MAPLE that respects utilization constraints, handles movable macros and guides the transition between global...
67
Voted
DAC
2003
ACM
15 years 10 months ago
2003
ACM
Partitioning an application among software running on a microprocessor and hardware co-processors in on-chip configurable logic has been shown to improve performance and energy co...
ISPD
2005
ACM
15 years 3 months ago
2005
ACM
In this paper, we present a very fast and accurate rectilinear Steiner minimal tree (RSMT)1 algorithm called FLUTE. The algorithm is an extension of the wirelength estimation appr...