261 search results - page 19 / 53 » SAT-Based Algorithms for Logic Minimization |
GLVLSI
2008
IEEE
15 years 4 months ago
2008
IEEE
Timing optimizations during logic synthesis has become a necessary step to achieve timing closure in VLSI designs. This often involves “shortening” all paths found in the circ...
FPGA
2001
ACM
15 years 2 months ago
2001
ACM
Conventional technology mapping algorithms for SRAM-based Field Programmable Gate Arrays (FPGAs) are normally carried out on a fixed logic decomposition of a circuit. The impact o...
MST
2006
14 years 9 months ago
2006
The "regularity" of a Boolean function can be exploited for decreasing its minimization time. It has already been shown that the notion of autosymmetry is a valid measure...
APLAS
2000
ACM
15 years 2 months ago
2000
ACM
We have implemented Kima, an automated error correction system for concurrent logic programs. Kima corrects near-misses such as wrong variable occurrences in the absence of explici...
DAC
1999
ACM
15 years 10 months ago
1999
ACM
Partitioning and clustering are crucial steps in circuit layout for handling large scale designs enabled by the deep submicron technologies. Retiming is an important sequential lo...