261 search results - page 21 / 53 » SAT-Based Algorithms for Logic Minimization |
VLDB
1990
ACM
15 years 1 months ago
1990
ACM
In this paper, we present an efficient algorithm for managing replicated data. We impose a logical tree structure on the set of copies of an object. In a failurefree environment t...
ICCAD
2004
IEEE
15 years 6 months ago
2004
IEEE
— This paper presents two contributions. The first is an incremental placement algorithm for placement-aware logic synthesis along with a proof of optimality. The algorithm can ...
PDP
2003
IEEE
15 years 3 months ago
2003
IEEE
As general-purpose parallel computers are increasingly being used to speed up different VLSI applications, the development of parallel algorithms for circuit testing, logic minimi...
ASPDAC
1998
ACM
15 years 2 months ago
1998
ACM
—An AND-OR-EXOR network, where the output EXOR gate has only two inputs, is one of the simplest three-level architecture. This network realizes an EXOR of two sum-of-products exp...
DFT
1999
IEEE
15 years 2 months ago
1999
IEEE
The inherent redundancy and in-the-field reconfiguration capabilities of field programmable gate arrays (FPGAs) provide alternatives to integrated circuit redundancy-based fault r...