261 search results - page 23 / 53 » SAT-Based Algorithms for Logic Minimization |
DLOG
2008
15 years 4 days ago
2008
Abstract. In this paper, we propose a new method for revising terminologies in description logic-based ontologies. Our revision method is a reformulation of the kernel revision ope...
DAC
2008
ACM
15 years 10 months ago
2008
ACM
Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions un...
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CORR
2007
Springer
14 years 9 months ago
2007
Springer
The study of finite automata and regular languages is a privileged meeting point of algebra and logic. Since the work of Büchi, regular languages have been classified according ...
TCAD
1998
14 years 9 months ago
1998
—Conventional scan design imposes considerable area and delay overheads. To establish a scan chain in the test mode, multiplexers at the inputs of flip-flops and scan wires are...
DAC
2005
ACM
15 years 10 months ago
2005
ACM
In this paper we present a system level technique for mapping large, multiple-IP-block designs to channel-width constrained FPGAs. Most FPGA clustering tools [2, 3, 11] aim to red...