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» SAT-Based Algorithms for Logic Minimization
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DAC
2009
ACM
15 years 10 months ago
Handling don't-care conditions in high-level synthesis and application for reducing initialized registers
Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle ...
Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo
ATS
2000
IEEE
134views Hardware» more  ATS 2000»
15 years 2 months ago
Fsimac: a fault simulator for asynchronous sequential circuits
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, ...
BNCOD
2007
137views Database» more  BNCOD 2007»
14 years 11 months ago
Isolating Order Semantics in Order-Sensitive XQuery-to-SQL Translation
Order is essential for XML query processing. Efficient XML processing with order consideration over relational storage is non-trivial, especially for complex nested XQuery expressi...
Song Wang, Ling Wang, Elke A. Rundensteiner
EUSFLAT
2009
312views Fuzzy Logic» more  EUSFLAT 2009»
14 years 7 months ago
Forecasting Exchange Rates: A Neuro-Fuzzy Approach
This paper presents an adaptive neuro-fuzzy inference system (ANFIS) for USD/JPY exchange rates forecasting. Previous work often used time series techniques and neural networks (NN...
Meysam Alizadeh, Roy Rada, Akram Khaleghei Ghoshe ...
DATE
2008
IEEE
132views Hardware» more  DATE 2008»
15 years 4 months ago
Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay Budgeting
Power gating is one of the most effective techniques in reducing the standby leakage current of VLSI circuits. In this paper we introduce a new approach for sleep transistor sizin...
Ehsan Pakbaznia, Massoud Pedram