261 search results - page 45 / 53 » SAT-Based Algorithms for Logic Minimization |
ICCAD
2003
IEEE
15 years 6 months ago
2003
IEEE
Routing for FPGAs has been a very challenging problem due to the limitation of routing resources. Although the FPGA routing problem has been researched extensively, most algorithm...
ASE
2005
14 years 9 months ago
2005
Techniques for efficiently evaluating future time Linear Temporal Logic (abbreviated LTL) formulae on finite execution traces are presented. While the standard models of LTL are i...
DAC
2005
ACM
15 years 10 months ago
2005
ACM
The race conditions often limit the smallest feasible clock period that the optimal clock skew scheduling can achieve. Therefore, the combination of clock skew scheduling and dela...
DAC
2006
ACM
15 years 10 months ago
2006
ACM
With increasing aggregate off-chip bandwidths exceeding terabits/second (Tb/s), the power dissipation is a serious design consideration. Additionally, design of I/O links is const...
XSYM
2009
Springer
15 years 4 months ago
2009
Springer
Abstract. We propose a mapping from the Enhanced Entity Relationship conceptual model to the W3C XML Schema Language with the following properties: information and integrity constr...