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» SAT-Based Algorithms for Logic Minimization
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ICCAD
1999
IEEE
119views Hardware» more  ICCAD 1999»
15 years 2 months ago
Factoring logic functions using graph partitioning
Algorithmic logic synthesis is usually carried out in two stages, the independent stage where logic minimization is performed on the Boolean equations with no regard to physical p...
Martin Charles Golumbic, Aviad Mintz
VLSID
2002
IEEE
135views VLSI» more  VLSID 2002»
15 years 10 months ago
An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis
In this paper, we address the problem of power dissipation minimization in combinational circuits implemented using pass transistor logic (PTL). We transform the problem of power ...
Rupesh S. Shelar, Sachin S. Sapatnekar
DAC
2003
ACM
15 years 10 months ago
A transformation based algorithm for reversible logic synthesis
A digital combinational logic circuit is reversible if it maps each input pattern to a unique output pattern. Such circuits are of interest in quantum computing, optical computing...
D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck
ICCD
2004
IEEE
105views Hardware» more  ICCD 2004»
15 years 6 months ago
Circuit-Based Preprocessing of ILP and Its Applications in Leakage Minimization and Power Estimation
In this paper we discuss the application of circuit-based logical reasoning to simplify optimization problems expressed as integer linear programs (ILP) over circuit states. We de...
Donald Chai, Andreas Kuehlmann
DAC
2003
ACM
15 years 10 months ago
Large-scale SOP minimization using decomposition and functional properties
In some cases, minimum Sum-Of-Products (SOP) expressions of Boolean functions can be derived by detecting decomposition and observing the functional properties such as unateness, ...
Alan Mishchenko, Tsutomu Sasao