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DSN
2011
IEEE
13 years 11 months ago
LLS: Cooperative integration of wear-leveling and salvaging for PCM main memory
Phase change memory (PCM) has emerged as a promising technology for main memory due to many advan­ tages, such as better scalability, non-volatility and fast read access. However,...
Lei Jiang, Yu Du, Youtao Zhang, Bruce R. Childers,...
ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
15 years 4 months ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
APVIS
2004
15 years 1 months ago
High Resolution Scalable Displays: Manufacturing and Use
Tiling projectors provides an effective and easy option to increase screen space. Differences in projectors' components however contribute to non-uniformities in illumination...
Nicole Bordes, Bernard Pailthorpe
ISCA
2010
IEEE
222views Hardware» more  ISCA 2010»
15 years 1 months ago
Cohesion: a hybrid memory model for accelerators
Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to mana...
John H. Kelm, Daniel R. Johnson, William Tuohy, St...
GECCO
2006
Springer
164views Optimization» more  GECCO 2006»
15 years 3 months ago
Biobjective evolutionary and heuristic algorithms for intersection of geometric graphs
Wire routing in a VLSI chip often requires minimization of wire-length as well as the number of intersections among multiple nets. Such an optimization problem is computationally ...
Rajeev Kumar, Pramod Kumar Singh, Bhargab B. Bhatt...