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RTCSA
2007
IEEE
14 years 19 days ago
An MPSoC Performance Estimation Framework Using Transaction Level Modeling
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
Rabie Ben Atitallah, Smaïl Niar, Samy Meftali...
IEEEPACT
2005
IEEE
13 years 12 months ago
Maximizing CMP Throughput with Mediocre Cores
In this paper we compare the performance of area equivalent small, medium, and large-scale multithreaded chip multiprocessors (CMTs) using throughput-oriented applications. We use...
John D. Davis, James Laudon, Kunle Olukotun
DAC
2004
ACM
13 years 11 months ago
Extending the transaction level modeling approach for fast communication architecture exploration
System-on-Chip (SoC) designs are increasingly becoming more complex. Efficient on-chip communication architectures are critical for achieving desired performance in these systems....
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...
IPPS
2009
IEEE
14 years 1 months ago
Dynamic iterations for the solution of ordinary differential equations on multicore processors
In the past few years, there has been a trend of providing increased computing power through greater number of cores on a chip, rather than through higher clock speeds. In order t...
Yanan Yu, Ashok Srinivasan
VLSID
2005
IEEE
285views VLSI» more  VLSID 2005»
14 years 6 months ago
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan,...