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ISQED
2010
IEEE
194views Hardware» more  ISQED 2010»
14 years 1 months ago
Accelerating trace computation in post-silicon debug
— Post-silicon debug comprises a significant and highly variable fraction of the total development time for large chip designs. To accelerate post-silicon debug, BackSpace [1, 2...
Johnny J. W. Kuan, Steven J. E. Wilton, Tor M. Aam...
EUROPAR
2009
Springer
13 years 11 months ago
Towards Metaprogramming for Parallel Systems on a Chip
We demonstrate that the performance of commodity parallel systems significantly depends on low-level details, such as storage layout and iteration space mapping, which motivates t...
Lee W. Howes, Anton Lokhmotov, Alastair F. Donalds...
DAC
2010
ACM
13 years 6 months ago
A correlation-based design space exploration methodology for multi-processor systems-on-chip
Given the increasing complexity of multi-processor systems-onchip, a wide range of parameters must be tuned to find the best trade-offs in terms of the selected system figures of ...
Giovanni Mariani, Aleksandar Brankovic, Gianluca P...
IPPS
2005
IEEE
13 years 12 months ago
Predicting Cache Space Contention in Utility Computing Servers
The need to provide performance guarantee in high performance servers has long been neglected. Providing performance guarantee in current and future servers is difficult because ...
Yan Solihin, Fei Guo, Seongbeom Kim
DAC
2011
ACM
12 years 6 months ago
Supervised design space exploration by compositional approximation of Pareto sets
Technology scaling allows the integration of billions of transistors on the same die but CAD tools struggle in keeping up with the increasing design complexity. Design productivit...
Hung-Yi Liu, Ilias Diakonikolas, Michele Petracca,...