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VLSID
2005
IEEE
102views VLSI» more  VLSID 2005»
16 years 15 hour ago
Integrated On-Chip Storage Evaluation in ASIP Synthesis
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
DAC
2007
ACM
16 years 19 days ago
Layered Switching for Networks on Chip
We present and evaluate a novel switching mechanism called layered switching. Conceptually, the layered switching implements wormhole on top of virtual cut-through switching. To s...
Zhonghai Lu, Ming Liu, Axel Jantsch
RTSS
2008
IEEE
15 years 6 months ago
Priority Assignment for Real-Time Wormhole Communication in On-Chip Networks
—Wormhole switching with fixed priority preemption has been proposed as a possible solution for real-time on-chip communication. However, none of current priority assignment pol...
Zheng Shi, Alan Burns
ETS
2006
IEEE
119views Hardware» more  ETS 2006»
15 years 5 months ago
On-Chip Test Generation Using Linear Subspaces
A central problem in built-in self test (BIST) is how to efficiently generate a small set of test vectors that detect all targeted faults. We propose a novel solution that uses l...
Ramashis Das, Igor L. Markov, John P. Hayes
HPCA
2003
IEEE
16 years 5 hour ago
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
Wai Hong Ho, Timothy Mark Pinkston