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» SEU tolerant device, circuit and processor design
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DSN
2011
IEEE
13 years 9 months ago
Cross-layer resilience using wearout aware design flow
—As process technology shrinks devices, circuits experience accelerated wearout. Monitoring wearout will be critical for improving the efficiency of error detection and correctio...
Bardia Zandian, Murali Annavaram
CF
2004
ACM
15 years 3 months ago
Opportunities and challenges in application-tuned circuits and architectures based on nanodevices
Nanoelectronics research has primarily focused on devices. By contrast, not much has been published on innovations at higher layers: we know little about how to construct circuits...
Teng Wang, Zhenghua Qi, Csaba Andras Moritz
ETS
2010
IEEE
140views Hardware» more  ETS 2010»
14 years 10 months ago
Increasing reliability of programmable mixed-signal systems by applying design diversity redundancy
This paper explores the concept of design diversity redundancy applied to mixed-signal (MS) circuit blocks, as a proposal to increase system reliability. Three different implement...
Gabriel de M. Borges, Luiz F. Gonçalves, Ti...
CHES
2005
Springer
109views Cryptology» more  CHES 2005»
15 years 3 months ago
Security Evaluation Against Electromagnetic Analysis at Design Time
Electromagnetic analysis (EMA) can be used to compromise secret information by analysing the electric and/or magnetic fields emanating from a device. It follows differential power...
Huiyun Li, A. Theodore Markettos, Simon W. Moore
DAC
2009
ACM
15 years 10 months ago
Online cache state dumping for processor debug
Post-silicon processor debugging is frequently carried out in a loop consisting of several iterations of the following two key steps: (i) processor execution for some duration, fo...
Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishna...