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» SEU tolerant device, circuit and processor design
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1999
IEEE
14 years 9 months ago
The Network RamDisk: Using remote memory on heterogeneous NOWs
Efficient data storage, a major concern in the modern computer industry, is mostly provided today by the the traditional magnetic disk. Unfortunately the cost of a disk transfer m...
Michail Flouris, Evangelos P. Markatos
FPL
2009
Springer
107views Hardware» more  FPL 2009»
15 years 2 months ago
An FPGA based verification platform for HyperTransport 3.x
In this paper we present a verification platform designed for HyperTransport 3.x (HT3) applications. HyperTransport 3.x is a very low latency and high bandwidth chip-tochip interc...
Heiner Litz, Holger Fröning, Maximilian Th&uu...
HPCA
2006
IEEE
15 years 10 months ago
BulletProof: a defect-tolerant CMP switch architecture
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transie...
Kypros Constantinides, Stephen Plaza, Jason A. Blo...
TEI
2010
ACM
158views Hardware» more  TEI 2010»
15 years 4 months ago
ChainMail: a configurable multimodal lining to enable sensate surfaces and interactive objects
The ChainMail system is a scalable electronic sensate skin that is designed as a dense sensor network. ChainMail is built from small (1”x1”) rigid circuit boards attached to t...
Behram F. T. Mistree, Joseph A. Paradiso
ISLPED
2007
ACM
57views Hardware» more  ISLPED 2007»
14 years 11 months ago
Resource area dilation to reduce power density in throughput servers
Throughput servers using simultaneous multithreaded (SMT) processors are becoming an important paradigm with products such as Sun's Niagara and IBM Power5. Unfortunately, thr...
Michael D. Powell, T. N. Vijaykumar