103 search results - page 8 / 21 » SEU tolerant device, circuit and processor design |
GLVLSI
2010
IEEE
15 years 2 months ago
2010
IEEE
NBTI is one of the most important silicon reliability problems facing processor designers today. The impact of NBTI can be mitigated at both the circuit and microarchitecture leve...
DDECS
2007
IEEE
15 years 4 months ago
2007
IEEE
– The implementation and the fault simulation technique for the highly reliable digital design using two FPGAs under a processor control is presented. Two FPGAs are used for dupl...
AICCSA
2008
IEEE
14 years 11 months ago
2008
IEEE
Nanodevices based circuit design will be based on the acceptance that a high percentage of devices in the design will be defective. In this work, we investigate a defect tolerant ...
ISLPED
2003
ACM
15 years 3 months ago
2003
ACM
Ever shrinking device sizes and innovative micro-architectural and circuit design techniques have made it possible to have multi-million transistor systems running at multi-gigahe...
DSN
2007
IEEE
15 years 4 months ago
2007
IEEE
Synchronous circuits are typically clocked considering worst case timing paths so that timing errors are avoided under all circumstances. In the case of a pipelined processor, thi...