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» SEU tolerant device, circuit and processor design
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HPCA
2008
IEEE
15 years 10 months ago
Supporting highly-decoupled thread-level redundancy for parallel programs
The continued scaling of device dimensions and the operating voltage reduces the critical charge and thus natural noise tolerance level of transistors. As a result, circuits can p...
M. Wasiur Rashid, Michael C. Huang
IEEEPACT
2008
IEEE
15 years 4 months ago
Skewed redundancy
Technology scaling in integrated circuits has consistently provided dramatic performance improvements in modern microprocessors. However, increasing device counts and decreasing o...
Gordon B. Bell, Mikko H. Lipasti
ISQED
2007
IEEE
150views Hardware» more  ISQED 2007»
15 years 4 months ago
A Design Methodology for Matching Improvement in Bandgap References
Errors caused by tolerance variations and mismatches among components severely degrade the performance of integrated circuits. These random effects in process parameters significa...
Juan Pablo Martinez Brito, Hamilton Klimach, Sergi...
DAC
2006
ACM
15 years 10 months ago
Synthesis of high-performance packet processing pipelines
Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the featur...
Cristian Soviani, Ilija Hadzic, Stephen A. Edwards
MICRO
2008
IEEE
106views Hardware» more  MICRO 2008»
15 years 4 months ago
EVAL: Utilizing processors with variation-induced timing errors
Parameter variation in integrated circuits causes sections of a chip to be slower than others. If, to prevent any resulting timing errors, we design processors for worst-case para...
Smruti R. Sarangi, Brian Greskamp, Abhishek Tiwari...