Sciweavers

727 search results - page 47 / 146
» SIMPL: A System for Integrating Optimization Techniques
Sort
View
ASAP
1996
IEEE
145views Hardware» more  ASAP 1996»
15 years 4 months ago
A Synthesis System For Bus-Based Wavefront Array Architectures
A datapath synthesis system (DPSS) for a bus-based wavefront array architecture, called rDPA (reconfigurable datapath architecture), is presented. An internal data bus to the arra...
Reiner W. Hartenstein, Jürgen Becker, Michael...
ICDCS
2008
IEEE
15 years 6 months ago
stdchk: A Checkpoint Storage System for Desktop Grid Computing
— Checkpointing is an indispensable technique to provide fault tolerance for long-running high-throughput applications like those running on desktop grids. This paper argues that...
Samer Al-Kiswany, Matei Ripeanu, Sudharshan S. Vaz...
LCTRTS
2010
Springer
15 years 6 months ago
Versatile system-level memory-aware platform description approach for embedded MPSoCs
In this paper, we present a novel system modeling language which targets primarily the development of source-level multiprocessor memory aware optimizations. In contrast to previo...
Robert Pyka, Felipe Klein, Peter Marwedel, Stylian...
CODES
2003
IEEE
15 years 5 months ago
Design space minimization with timing and code size optimization for embedded DSP
One of the most challenging problems in high-level synthesis is how to quickly explore a wide range of design options to achieve high-quality designs. This paper presents an Integ...
Qingfeng Zhuge, Zili Shao, Bin Xiao, Edwin Hsing-M...
ISLPED
2006
ACM
145views Hardware» more  ISLPED 2006»
15 years 5 months ago
An optimal analytical solution for processor speed control with thermal constraints
As semiconductor manufacturing technology scales to smaller device sizes, the power consumption of clocked digital ICs begins to increase. Dynamic voltage and frequency scaling (D...
Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Ch...