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ISCA
2008
IEEE
113views Hardware» more  ISCA 2008»
15 years 10 months ago
A Two-Level Load/Store Queue Based on Execution Locality
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be incr...
Miquel Pericàs, Adrián Cristal, Fran...
DATE
2006
IEEE
84views Hardware» more  DATE 2006»
15 years 10 months ago
Vulnerability analysis of L2 cache elements to single event upsets
Memory elements are the most vulnerable system component to soft errors. Since memory elements in cache arrays consume a large fraction of the die in modern microprocessors, the p...
Hossein Asadi, Vilas Sridharan, Mehdi Baradaran Ta...
ISLPED
2005
ACM
102views Hardware» more  ISLPED 2005»
15 years 9 months ago
Snug set-associative caches: reducing leakage power while improving performance
As transistors keep shrinking and on-chip data caches keep growing, static power dissipation due to leakage of caches takes an increasing fraction of total power in processors. Se...
Jia-Jhe Li, Yuan-Shin Hwang
ECML
2005
Springer
15 years 9 months ago
Kernel Basis Pursuit
ABSTRACT. Estimating a non-uniformly sampled function from a set of learning points is a classical regression problem. Kernel methods have been widely used in this context, but eve...
Vincent Guigue, Alain Rakotomamonjy, Stépha...
ICPP
2003
IEEE
15 years 9 months ago
A Hardware-based Cache Pollution Filtering Mechanism for Aggressive Prefetches
Aggressive hardware-based and software-based prefetch algorithms for hiding memory access latencies were proposed to bridge the gap of the expanding speed disparity between proces...
Xiaotong Zhuang, Hsien-Hsin S. Lee