35 search results - page 4 / 7 » SOI Transistor Model for Fast Transient Simulation |
VLSID
2007
IEEE
15 years 10 months ago
2007
IEEE
Accurate electrical masking modeling represents a significant challenge in soft error rate analysis for combinational logic circuits. In this paper, we use table lookup MOSFET mode...
ISPASS
2009
IEEE
15 years 4 months ago
2009
IEEE
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
124
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ICCAD
2003
IEEE
15 years 6 months ago
2003
IEEE
This paper proposes a model for calculating statistical gate-delay variation caused by intra-chip and inter-chip variability. As the variation of individual gate delays directly i...
109
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SIGMETRICS
2003
ACM
15 years 2 months ago
2003
ACM
In this paper we present a general hybrid systems modeling framework to describe the flow of traffic in communication networks. To characterize network behavior, these models use...
DAC
2000
ACM
15 years 1 months ago
2000
ACM
The decrease in feature size and added chip functionality in large sub-micron integrated circuits demand larger grids for power distribution. Since power grids are performance lim...