97 search results - page 18 / 20 » SRAM Cell Current in Low Leakage Design |
DAC
2006
ACM
16 years 19 days ago
2006
ACM
As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people oft...
89
Voted
VLSID
2006
IEEE
16 years 1 days ago
2006
IEEE
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
103
Voted
TVLSI
2010
14 years 6 months ago
2010
Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise mar...
ISCA
2010
IEEE
15 years 3 months ago
2010
IEEE
As leakage and other charge storage limitations begin to impair the scalability of DRAM, non-volatile resistive memories are being developed as a potential replacement. Unfortunat...
83
Voted
ASPDAC
2009
ACM
15 years 4 months ago
2009
ACM
— In three-dimensional (3D) chips, the amount of supply current per package pin is significantly more than in two-dimensional (2D) designs. Therefore, the power supply noise pro...