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» SRAM Cell Current in Low Leakage Design
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ITC
1997
IEEE
107views Hardware» more  ITC 1997»
15 years 3 months ago
Weak Write Test Mode: An SRAM Cell Stability Design for Test Technique
The detection of cell stability and data retention faults in SRAMs has been a time consuming process. In this paper we discuss a new design for test technique called Weak Write Tes...
Anne Meixner, Jash Banik
TVLSI
2010
14 years 6 months ago
SRAM Read/Write Margin Enhancements Using FinFETs
Process-induced variations and sub-threshold leakage in bulk-Si technology limit the scaling of SRAM into sub-32 nm nodes. New device architectures are being considered to improve ...
Andrew Carlson, Zheng Guo, Sriram Balasubramanian,...
HPCA
2011
IEEE
14 years 3 months ago
Archipelago: A polymorphic cache design for enabling robust near-threshold operation
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
ASPDAC
2004
ACM
126views Hardware» more  ASPDAC 2004»
15 years 5 months ago
High-level area and power-up current estimation considering rich cell library
— Reducing the ever-growing leakage power is critical to power efficient designs. Leakage reduction techniques such as power-gating using sleep transistor insertion introduces la...
Fei Li, Lei He, Joseph M. Basile, Rakesh J. Patel,...
ISCA
2002
IEEE
96views Hardware» more  ISCA 2002»
15 years 4 months ago
Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines
Leakage power is dominated by critical paths, and hence dynamic deactivation of fast transistors can yield large savings. We introduce metrics for comparing fine-grain dynamic de...
Seongmoo Heo, Kenneth C. Barr, Mark Hampton, Krste...