314 search results - page 14 / 63 » Sanity Checks in Formal Verification |
ICSE
2008
IEEE-ACM
15 years 10 months ago
2008
IEEE-ACM
Automatically detecting bugs in programs has been a long-held goal in software engineering. Many techniques exist, trading-off varying levels of automation, thoroughness of covera...
FMCAD
2007
Springer
15 years 1 months ago
2007
Springer
Abstract--Analog and mixed signal (AMS) designs are important integrated circuits that are usually needed at the interface between the electronic system and the real world. Recentl...
ATVA
2009
Springer
15 years 1 months ago
2009
Springer
We present a framework for certifying hardware designs generated through behavioral synthesis, by using formal verification to certify the associated synthesis transformations. We ...
CAI
2006
Springer
14 years 9 months ago
2006
Springer
In this paper, formal verification methodologies and the SPR (Safety Problem Resolver) model checking tool are used for verifying a security model's safety. The SPR tool makes...
ICESS
2005
Springer
15 years 3 months ago
2005
Springer
PeaCE(Ptolemy extension as a Codesign Environment) was developed for the hardware and software codesign framework which allows us to express both data flow and control flow. The fF...