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» Sanity Checks in Formal Verification
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FSEN
2009
Springer
15 years 1 months ago
Verification, Performance Analysis and Controller Synthesis for Real-Time Systems
This note aims at providing a concise and precise Travellers Guide, Phrase Book or Reference Manual to the timed automata modeling formalism introduced by Alur and Dill [7, 8]. The...
Uli Fahrenberg, Kim G. Larsen, Claus R. Thrane
PTS
2000
99views Hardware» more  PTS 2000»
14 years 11 months ago
Verification of Test Suites
We present a formal approach to check the correctness and to propose corrections of hand-written test suites with respect to a formal specification of the protocol implementations ...
Claude Jard, Thierry Jéron, Pierre Morel
ISCAS
2003
IEEE
89views Hardware» more  ISCAS 2003»
15 years 2 months ago
Synthesizing checkers for on-line verification of System-on-Chip designs
In modern System-on-Chip (SoC) designs verification becomes the major bottleneck. Since by using state-of-theart techniques complete designs cannot be fully formally verified, it ...
Rolf Drechsler
JOT
2008
200views more  JOT 2008»
14 years 9 months ago
Applying Model Checking to Concurrent UML Models
We present, in this paper, a framework supporting a formal verification of concurrent UML models using the Maude language. We consider both static and dynamic features of concurre...
Patrice Gagnon, Farid Mokhati, Mourad Badri
120
Voted
CIBSE
2008
ACM
14 years 11 months ago
Using Refinement Checking as System Testing
Abstract. Software testing is an expensive and time-consuming activity; it is also error-prone due to human factors. But, it still is the most common effort used in the software in...
Cristiano Bertolini, Alexandre Mota