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» Sanity Checks in Formal Verification
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DAC
2009
ACM
16 years 25 days ago
Computing bounds for fault tolerance using formal techniques
Continuously shrinking feature sizes result in an increasing susceptibility of circuits to transient faults, e.g. due to environmental radiation. Approaches to implement fault tol...
André Sülflow, Görschwin Fey, Rol...
WWW
2002
ACM
16 years 15 days ago
Model checking cobweb protocols for verification of HTML frames behavior
HTML documents composed of frames can be difficult to write correctly. We demonstrate a technique that can be used by authors manually creating HTML documents (or by document edit...
P. David Stotts, Jaime Navon
SIGSOFT
2007
ACM
16 years 17 days ago
The symmetry of the past and of the future: bi-infinite time in the verification of temporal properties
Model checking techniques have traditionally dealt with temporal logic languages and automata interpreted over -words, i.e., infinite in the future but finite in the past. However...
Matteo Pradella, Angelo Morzenti, Pierluigi San Pi...
ENTCS
2006
109views more  ENTCS 2006»
14 years 12 months ago
Incremental Verification for On-the-Fly Controller Synthesis
The CIRCA system automatically synthesizes hard real-time discrete event controllers from plant and environment descriptions. CIRCA's automatically-synthesized controllers pr...
David J. Musliner, Michael J. S. Pelican, Robert P...
SAC
2010
ACM
14 years 9 months ago
A machine-checked soundness proof for an efficient verification condition generator
Verification conditions (VCs) are logical formulae whose validity implies the correctness of a program with respect to a specification. The technique of checking software properti...
Frédéric Vogels, Bart Jacobs 0002, F...