314 search results - page 27 / 63 » Sanity Checks in Formal Verification |
107
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VMCAI
2010
Springer
15 years 7 months ago
2010
Springer
In the recent years, there have been a large amount of investigations on safety verification of uncertain continuous systems. In engineering and applied mathematics, this verificat...
102
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ACMICEC
2007
ACM
15 years 1 months ago
2007
ACM
Norms defined by institutions and enforced by organizations have been put forward as a mechanism to increase the efficiency and reliability of electronic transactions carried out ...
CADE
2007
Springer
15 years 10 months ago
2007
Springer
In this paper, a proof assistant, called SAD, is presented. SAD deals with mathematical texts that are formalized in the ForTheL language (brief description of which is also given)...
100
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FMICS
2006
Springer
15 years 1 months ago
2006
Springer
Abstract. Bounded model checking (BMC) based on satisfiability testing (SAT) has been introduced as a complementary technique to BDDbased symbolic model checking of LTL properties ...
67
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IEEEPACT
2007
IEEE
15 years 4 months ago
2007
IEEE
The process of verifying a new microprocessor is a major problem for the computer industry. Currently, architects design processors to be fast, power-efficient, and reliable. Howe...