314 search results - page 32 / 63 » Sanity Checks in Formal Verification |
ATVA
2006
Springer
15 years 1 months ago
2006
Springer
Of special interest in formal verification are safety properties, which assert that the system always stays within some allowed region. Each safety property can be associated with...
CADE
2008
Springer
15 years 10 months ago
2008
Springer
We present a tool for automatic generation of packed bitfields and tagged unions for systems-level C, along with automatic, machine checked refinement proofs in Isabelle/HOL. Our a...
WWW
2005
ACM
15 years 10 months ago
2005
ACM
We present a design for verification approach to developing reliable web services. We focus on composite web services which consist of asynchronously communicating peers. Our goal...
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FORMATS
2004
Springer
15 years 3 months ago
2004
Springer
For successful software verification, model checkers must be capable of handling a large number of program variables. Traditional, BDD-based model checking is deficient in this reg...
105
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DAC
2007
ACM
15 years 1 months ago
2007
ACM
When designers create RTL models from a system-level specification, arrays in the system-level model are often implemented as memories in the RTL. Knowing the correspondence betwe...