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» Sanity Checks in Formal Verification
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CODES
2008
IEEE
14 years 11 months ago
Model checking SystemC designs using timed automata
SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In...
Paula Herber, Joachim Fellmuth, Sabine Glesner
CAISE
2010
Springer
14 years 10 months ago
Design and Verification of Instantiable Compliance Rule Graphs in Process-Aware Information Systems
For enterprises it has become crucial to check compliance of their business processes with certain rules such as medical guidelines or financial regulations. When automating compli...
Linh Thao Ly, Stefanie Rinderle-Ma, Peter Dadam
PROCOMET
1998
14 years 11 months ago
Extended static checking
Software development and maintenance are costly endeavors. The cost can be reduced if more software defects are detected earlier in the development cycle. This paper introduces th...
K. Rustan M. Leino
CAV
2006
Springer
132views Hardware» more  CAV 2006»
15 years 1 months ago
Symmetry Reduction for Probabilistic Model Checking
We present an approach for applying symmetry reduction techniques to probabilistic model checking, a formal verification method for the quantitative analysis of systems with stocha...
Marta Z. Kwiatkowska, Gethin Norman, David Parker
85
Voted
FC
2010
Springer
169views Cryptology» more  FC 2010»
15 years 1 months ago
A Formal Approach for Automated Reasoning about Off-Line and Undetectable On-Line Guessing
Abstract. Starting from algebraic properties that enable guessing lowentropy secrets, we formalize guessing rules for symbolic verification. The rules are suited for both off-line ...
Bogdan Groza, Marius Minea