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» Sanity Checks in Formal Verification
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COMPSAC
2007
IEEE
15 years 1 months ago
Unified Property Specification for Hardware/Software Co-Verification
Hardware/software co-verification is becoming an indispensable tool for building highly trustworthy embedded systems. A stumbling block to effective co-verification using model ch...
Fei Xie, Huaiyu Liu
SIGSOFT
2005
ACM
15 years 10 months ago
Fluent temporal logic for discrete-time event-based models
Fluent model checking is an automated technique for verifying that an event-based operational model satisfies some state-based declarative properties. The link between the event-b...
Emmanuel Letier, Jeff Kramer, Jeff Magee, Sebasti&...
DSN
2004
IEEE
15 years 1 months ago
Verifying Web Applications Using Bounded Model Checking
The authors describe the use of bounded model checking (BMC) for verifying Web application code. Vulnerable sections of code are patched automatically with runtime guards, allowin...
Yao-Wen Huang, Fang Yu, Christian Hang, Chung-Hung...
ARTS
1999
Springer
15 years 1 months ago
ProbVerus: Probabilistic Symbolic Model Checking
Model checking can tell us whether a system is correct; probabilistic model checking can also tell us whether a system is timely and reliable. Moreover, probabilistic model checkin...
Vicky Hartonas-Garmhausen, Sérgio Vale Agui...
DAC
2002
ACM
15 years 10 months ago
High-Level specification and automatic generation of IP interface monitors
A central problem in functional verification is to check that a circuit block is producing correct outputs while enforcing that the environment is providing legal inputs. To attac...
Marcio T. Oliveira, Alan J. Hu