314 search results - page 48 / 63 » Sanity Checks in Formal Verification |
102
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TCAD
2008
14 years 11 months ago
2008
Due to the increasing abstraction gap between the initial system model and a final implementation, the verification of the respective models against each other is a formidable task...
KBSE
1998
IEEE
15 years 4 months ago
1998
IEEE
Most efforts to automate formal verification of communicating systems have centred around finite-state systems (FSSs). However, FSSs are incapable of modelling many practical comm...
COORDINATION
2009
Springer
16 years 11 days ago
2009
Springer
Process algebras are a set of mathematically rigourous languages with well defined semantics that permit modelling behaviour of concurrent and communicating systems. Verification o...
ATAL
2010
Springer
15 years 17 hour ago
2010
Springer
ATL+ is a variant of alternating-time temporal logic that does not have the expressive power of full ATL , but still allows for expressing some natural properties of agents. It ha...
119
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ICCTA
2007
IEEE
15 years 3 months ago
2007
IEEE
The variables of the high-level specifications and the automatically generated temporary variables are mapped on to the data-path registers during data-path synthesis phase of hig...