314 search results - page 54 / 63 » Sanity Checks in Formal Verification |
CADE
2007
Springer
15 years 10 months ago
2007
Springer
Abstract. First order logic provides a convenient formalism for describing a wide variety of verification conditions. Two main approaches to checking such conditions are pure first...
MICRO
2008
IEEE
14 years 9 months ago
2008
IEEE
Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to ...
DAC
2009
ACM
15 years 10 months ago
2009
ACM
Boolean satisfiability (SAT) solvers are used heavily in hardware and software verification tools for checking satisfiability of Boolean formulas. Most state-of-the-art SAT solver...
CADE
2008
Springer
15 years 10 months ago
2008
Springer
Tree automata completion is a technique for the verification of infinite state systems. It has already been used for the verification of cryptographic protocols and the prototyping...
DAC
2007
ACM
15 years 1 months ago
2007
ACM
We present a framework for validating the compliance of a design with a given architecture. Our approach is centered on the concept of misinterpretations. These include missing be...