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» Satellite Data Exploitation Design Architecture
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IESS
2007
Springer
165views Hardware» more  IESS 2007»
15 years 4 months ago
Data Reuse Driven Memory and Network-On-Chip Co-Synthesis
NoCs present a possible communication infrastructure solution to deal with increased design complexity and shrinking time-to-market. The communication infrastructure is a signific...
Ilya Issenin, Nikil Dutt
MICRO
2008
IEEE
139views Hardware» more  MICRO 2008»
15 years 4 months ago
Adaptive data compression for high-performance low-power on-chip networks
With the recent design shift towards increasing the number of processing elements in a chip, high-bandwidth support in on-chip interconnect is essential for low-latency communicat...
Yuho Jin, Ki Hwan Yum, Eun Jung Kim
76
Voted
DAC
2003
ACM
15 years 11 months ago
Symbolic representation with ordered function templates
Binary Decision Diagrams (BDDs) often fail to exploit sharing between Boolean functions that differ only in their support variables. In a memory circuit, for example, the function...
Amit Goel, Gagan Hasteer, Randal E. Bryant
85
Voted
ISCA
2010
IEEE
176views Hardware» more  ISCA 2010»
15 years 2 months ago
Forwardflow: a scalable core for power-constrained CMPs
Chip Multiprocessors (CMPs) are now commodity hardware, but commoditization of parallel software remains elusive. In the near term, the current trend of increased coreper-socket c...
Dan Gibson, David A. Wood
76
Voted
DAC
2000
ACM
15 years 11 months ago
Convex delay models for transistor sizing
This paper derives a methodology for developing accurate convex delay models to be used for transistor sizing. A new rich class of convex functions to model gate delay is presente...
Mahesh Ketkar, Kishore Kasamsetty, Sachin S. Sapat...