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» Satellite Data Exploitation Design Architecture
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ANCS
2009
ACM
14 years 8 months ago
Design and performance analysis of a DRAM-based statistics counter array architecture
The problem of maintaining efficiently a large number (say millions) of statistics counters that need to be updated at very high speeds (e.g. 40 Gb/s) has received considerable re...
Haiquan (Chuck) Zhao, Hao Wang, Bill Lin, Jun (Jim...
MICRO
2005
IEEE
130views Hardware» more  MICRO 2005»
15 years 3 months ago
Exploiting Vector Parallelism in Software Pipelined Loops
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasin...
JCDL
2006
ACM
141views Education» more  JCDL 2006»
15 years 4 months ago
An architecture for the aggregation and analysis of scholarly usage data
Although recording of usage data is common in scholarly information services, its exploitation for the creation of valueadded services remains limited due to concerns regarding, a...
Johan Bollen, Herbert Van de Sompel
MICRO
2007
IEEE
184views Hardware» more  MICRO 2007»
15 years 4 months ago
Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures
The recent design shift towards multicore processors has spawned a significant amount of research in the area of program parallelization. The future abundance of cores on a singl...
Michael L. Chu, Rajiv A. Ravindran, Scott A. Mahlk...
SBACPAD
2007
IEEE
121views Hardware» more  SBACPAD 2007»
15 years 4 months ago
DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems
One way to exploit Thread Level Parallelism (TLP) is to use architectures that implement novel multithreaded execution models, like Scheduled DataFlow (SDF). This latter model pro...
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic