160 search results - page 11 / 32 » Satisfiability-Based Algorithms for Boolean Optimization |
FPGA
2007
ACM
15 years 4 months ago
2007
ACM
Boolean matching (BM) is a widely used technique in FPGA resynthesis and architecture evaluation. In this paper we present several improvements to the recently proposed SAT-based ...
CEC
2008
IEEE
15 years 4 months ago
2008
IEEE
Abstract— This paper explores the idea of neutrality in heuristic optimization algorithms. In particular, the effect of having multiple levels of neutrality in representations is...
EVOW
2004
Springer
15 years 3 months ago
2004
Springer
Recently, an approach has been presented to minimize Disjoint Sumof-Products (DSOPs) based on Binary Decision Diagrams (BDDs). Due to the symbolic representation of cubes for larg...
TAMC
2010
Springer
15 years 2 months ago
2010
Springer
Unless we resolve the P vs NP question, we are unable to say whether there is an algorithm (acceptor) that accepts Boolean tautologies in polynomial time and does not accept non-ta...
GLVLSI
2009
IEEE
15 years 4 months ago
2009
IEEE
Logic decomposition has been extensively used to optimize the worst-case delay and the area in the technology independent phase. Bi-decomposition is one of the state-of-art techni...