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103
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HPCC
2009
Springer
15 years 4 months ago
Dynamically Filtering Thread-Local Variables in Lazy-Lazy Hardware Transactional Memory
Abstract--Transactional Memory (TM) is an emerging technology which promises to make parallel programming easier. However, to be efficient, underlying TM system should protect only...
Sutirtha Sanyal, Sourav Roy, Adrián Cristal...
LCPC
2005
Springer
15 years 6 months ago
Titanium Performance and Potential: An NPB Experimental Study
Titanium is an explicitly parallel dialect of JavaTM designed for high-performance scientific programming. It offers objectorientation, strong typing, and safe memory management...
Kaushik Datta, Dan Bonachea, Katherine A. Yelick
IPPS
1999
IEEE
15 years 4 months ago
Application of Parallel Processors to Real-Time Sensor Array Processing
Historically, most radar sensor array processing has been implemented using dedicated and specialized processing systems. This approach was necessary because the algorithm computa...
David R. Martinez
108
Voted
SBACPAD
2007
IEEE
121views Hardware» more  SBACPAD 2007»
15 years 6 months ago
DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems
One way to exploit Thread Level Parallelism (TLP) is to use architectures that implement novel multithreaded execution models, like Scheduled DataFlow (SDF). This latter model pro...
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic
79
Voted
ICSE
2007
IEEE-ACM
16 years 18 days ago
DECKARD: Scalable and Accurate Tree-Based Detection of Code Clones
Detecting code clones has many software engineering applications. Existing approaches either do not scale to large code bases or are not robust against minor code modifications. I...
Ghassan Misherghi, Lingxiao Jiang, Stéphane...