958 search results - page 189 / 192 » Scalable Performance of the Panasas Parallel File System |
122
Voted
SIAMSC
2008
15 years 1 months ago
2008
Abstract. A model for the flow of calcium in an atrial heart cell is given by a system of timedependent reaction-diffusion equations coupled by non-linear reaction terms. Calcium i...
140
Voted
PPL
2008
15 years 1 months ago
2008
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
113
Voted
TC
2008
15 years 1 months ago
2008
To support dynamic address translation in today's microprocessors, the first-level cache is accessed in parallel with a translation lookaside buffer (TLB). However, this curre...
110
Voted
HPCA
2009
IEEE
16 years 1 months ago
2009
IEEE
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...
110
Voted
AINA
2009
IEEE
15 years 8 months ago
2009
IEEE
The architectures which support modern supercomputing machinery are as diverse today, as at any point during the last twenty years. The variety of processor core arrangements, thr...