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ISCA
2011
IEEE
229views Hardware» more  ISCA 2011»
14 years 7 months ago
TLSync: support for multiple fast barriers using on-chip transmission lines
As the number of cores on a single-chip grows, scalable barrier synchronization becomes increasingly difficult to implement. In software implementations, such as the tournament ba...
Jungju Oh, Milos Prvulovic, Alenka G. Zajic
ASPLOS
2009
ACM
16 years 4 months ago
Maximum benefit from a minimal HTM
A minimal, bounded hardware transactional memory implementation significantly improves synchronization performance when used in an operating system kernel. We add HTM to Linux 2.4...
Owen S. Hofmann, Christopher J. Rossbach, Emmett W...
140
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COORDINATION
2009
Springer
16 years 4 months ago
Multicore Scheduling for Lightweight Communicating Processes
Process-oriented programming is a design methodology in which software applications are constructed from communicating concurrent processes. A process-oriented design is typically ...
Carl G. Ritson, Adam T. Sampson, Fred R. M. Barnes
ICSE
2004
IEEE-ACM
16 years 3 months ago
Architecting and Implementing Versatile Dependability
Distributed applications must often consider and select the appropriate trade-offs among three important aspects ? fault-tolerance, performance and resources. We introduce a novel ...
Tudor Dumitras, Deepti Srivastava, Priya Narasimha...
ESSOS
2010
Springer
16 years 20 days ago
Experiences with PDG-Based IFC
Information flow control systems provide the guarantees that are required in today’s security-relevant systems. While the literature has produced a wealth of techniques to ensur...
Christian Hammer