The scheduling of exams in institutions of higher education is known to be a highly constrained problem. The advent of modularity in many institutions in the UK has resulted in a s...
We describe a programming framework for high performance clusters with various hardware accelerators. In this framework, users can utilize the available heterogeneous resources pr...
Kuen Hung Tsoi, Anson H. T. Tse, Peter Pietzuch, W...
This paper proposes a robust real-time, scalable and modular Field Programmable Gate Array (FPGA) based implementation of a spatiotemporal segmentation of video objects. The goal ...
In this paper we present a full-custom VLSI design of highspeed 2-D DCT/IDCT processor based on the new class of time-recursive algorithms and architectures which has never been i...
Data races occur when multiple threads are about to access the same piece of memory, and at least one of those accesses is a write. Such races can lead to hard-to-reproduce bugs t...