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ISCA
2006
IEEE
92views Hardware» more  ISCA 2006»
15 years 1 months ago
Quantum Memory Hierarchies: Efficient Designs to Match Available Parallelism in Quantum Computing
The assumption of maximum parallelism support for the successful realization of scalable quantum computers has led to homogeneous, "sea-of-qubits" architectures. The res...
Darshan D. Thaker, Tzvetan S. Metodi, Andrew W. Cr...
DAC
2008
ACM
16 years 2 months ago
Latency and bandwidth efficient communication through system customization for embedded multiprocessors
We present a cross-layer customization methodology for latency and bandwidth efficient inter-core communication in embedded multiprocessors. The methodology integrates compiler, o...
Chenjie Yu, Peter Petrov
SIGMOD
1997
ACM
134views Database» more  SIGMOD 1997»
15 years 5 months ago
Scalable Parallel Data Mining for Association Rules
One of the important problems in data mining is discovering association rules from databases of transactions where each transaction consists of a set of items. The most time consu...
Eui-Hong Han, George Karypis, Vipin Kumar
MICRO
2010
IEEE
170views Hardware» more  MICRO 2010»
14 years 11 months ago
Tolerating Concurrency Bugs Using Transactions as Lifeguards
Abstract--Parallel programming is hard, because it is impractical to test all possible thread interleavings. One promising approach to improve a multi-threaded program's relia...
Jie Yu, Satish Narayanasamy
DATE
2003
IEEE
112views Hardware» more  DATE 2003»
15 years 6 months ago
Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0
The concept of a SOC platform architecture introduces the concept of a communication infrastructure. In the transaction-level a finite set of architecture components (memories, ar...
Marco Caldari, Massimo Conti, Massimo Coppola, Ste...