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SIGGRAPH
2000
ACM
15 years 2 months ago
Pomegranate: a fully scalable graphics architecture
Pomegranate is a parallel hardware architecture for polygon rendering that provides scalable input bandwidth, triangle rate, pixel rate, texture memory and display bandwidth while...
Matthew Eldridge, Homan Igehy, Pat Hanrahan
TCOS
2010
14 years 4 months ago
PET SNAKE: A Special Purpose Architecture to Implement an Algebraic Attack in Hardware
Abstract. In [24] Raddum and Semaev propose a technique to solve systems of polynomial equations over F2 as occurring in algebraic attacks on block ciphers. This approach is known ...
Willi Geiselmann, Kenneth Matheis, Rainer Steinwan...
ICCD
2004
IEEE
138views Hardware» more  ICCD 2004»
15 years 6 months ago
Design and Implementation of Scalable Low-Power Montgomery Multiplier
In this paper, an efficient Montgomery multiplier is introduced for the modular exponentiation operation, which is fundamental to numerous public-key cryptosystems. Four aspects a...
Hee-Kwan Son, Sang-Geun Oh
MICRO
2007
IEEE
188views Hardware» more  MICRO 2007»
15 years 4 months ago
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding
In deep sub-micron ICs, growing amounts of ondie memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. As scaling progresses...
Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Fal...
LCTRTS
2010
Springer
14 years 7 months ago
Compiler directed network-on-chip reliability enhancement for chip multiprocessors
Chip multiprocessors (CMPs) are expected to be the building blocks for future computer systems. While architecting these emerging CMPs is a challenging problem on its own, program...
Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin,...