162 search results - page 18 / 33 » Scalable and reliable communication for hardware transaction... |
100
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MICRO
2010
IEEE
14 years 8 months ago
2010
IEEE
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
ISQED
2008
IEEE
15 years 4 months ago
2008
IEEE
We propose a novel dependable SRAM with 7T memory cells, and introduce a new concept, “quality of a bit (QoB)” for it. The proposed SRAM has three modes: a typical mode, high-...
101
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ISCA
1998
IEEE
15 years 2 months ago
1998
IEEE
Computer systems have become powerful enough to process continuous data streams such as video or animated graphics. While processing power and communication bandwidth of today...
SOSP
2009
ACM
15 years 6 months ago
2009
ACM
Commodity computer systems contain more and more processor cores and exhibit increasingly diverse architectural tradeoffs, including memory hierarchies, interconnects, instructio...
104
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FPL
2006
Springer
15 years 1 months ago
2006
Springer
The recent development of Platform-FPGA or FieldProgrammable System-on-Chip architectures, with immersed coarse-grain processors, embedded memories and IP cores, offers the potent...