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CODES
2003
IEEE
15 years 3 months ago
Schedule-aware performance estimation of communication architecture for efficient design space exploration
In this paper, we are concerned about the performance estimation of bus-based architectures assuming that the task partitioning on the processing components is already determined....
Sungchan Kim, Chaeseok Im, Soonhoi Ha
SIGCOMM
2000
ACM
15 years 1 months ago
Memory-efficient state lookups with fast updates
Routers must do a best matching pre x lookup for every packet solutions for Gigabit speeds are well known. As Internet link speeds higher, we seek a scalable solution whose speed ...
Sandeep Sikka, George Varghese
ISCA
1998
IEEE
114views Hardware» more  ISCA 1998»
15 years 2 months ago
The MIT Alewife Machine: Architecture and Performance
Alewife is a multiprocessor architecture that supports up to 512 processing nodes connected over a scalable and cost-effective mesh network at a constant cost per node. The MIT Al...
Anant Agarwal, Ricardo Bianchini, David Chaiken, K...
SENSYS
2004
ACM
15 years 3 months ago
Hardware design experiences in ZebraNet
The enormous potential for wireless sensor networks to make a positive impact on our society has spawned a great deal of research on the topic, and this research is now producing ...
Pei Zhang, Christopher M. Sadler, Stephen A. Lyon,...
DATE
2006
IEEE
134views Hardware» more  DATE 2006»
15 years 3 months ago
ASIP-based multiprocessor SoC design for simple and double binary turbo decoding
This paper presents a new multiprocessor platform for high throughput turbo decoding. The proposed platform is based on a new configurable ASIP combined with an efficient memory a...
Olivier Muller, Amer Baghdadi, Michel Jéz&e...