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125
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MICRO
2010
IEEE
156views Hardware» more  MICRO 2010»
14 years 11 months ago
Explicit Communication and Synchronization in SARC
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
Manolis Katevenis, Vassilis Papaefstathiou, Stamat...
105
Voted
PVLDB
2010
204views more  PVLDB 2010»
14 years 11 months ago
Cheetah: A High Performance, Custom Data Warehouse on Top of MapReduce
Large-scale data analysis has become increasingly important for many enterprises. Recently, a new distributed computing paradigm, called MapReduce, and its open source implementat...
Songting Chen
106
Voted
DLOG
2010
14 years 10 months ago
TBox Classification in Parallel: Design and First Evaluation
Abstract. One of the most frequently used inference services of description logic reasoners classifies all named classes of OWL ontologies into a subsumption hierarchy. Due to emer...
Mina Aslani, Volker Haarslev
99
Voted
MICRO
2010
IEEE
270views Hardware» more  MICRO 2010»
14 years 10 months ago
Many-Thread Aware Prefetching Mechanisms for GPGPU Applications
Abstract-- We consider the problem of how to improve memory latency tolerance in massively multithreaded GPGPUs when the thread-level parallelism of an application is not sufficien...
Jaekyu Lee, Nagesh B. Lakshminarayana, Hyesoon Kim...
OPODIS
2010
14 years 10 months ago
An Adaptive Technique for Constructing Robust and High-Throughput Shared Objects
Abstract. Shared counters are the key to solving a variety of coordination problems on multiprocessor machines, such as barrier synchronization and index distribution. It is desire...
Danny Hendler, Shay Kutten, Erez Michalak